HY5PS1G831CFP-S6

Product Summary

The HY5PS1G831CFP-S6 is a 1Gb DDR2 SDRAM.

Parametrics

HY5PS1G831CFP-S6 absolute maximum ratings: (1)Voltage on VDD pin relative to Vss: - 1.0 V to 2.3 V; (2)Voltage on VDDQ pin relative to Vss: - 0.5 V to 2.3 V; (3)Voltage on VDDL pin relative to Vss: - 0.5 V to 2.3 V; (4)Voltage on any pin relative to Vss: - 0.5 V to 2.3 V; (5)Storage Temperature: -55 to +100 °C; (6)Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V): -2 uA to 2 uA; (7)Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled: -5 uA to 5 uA.

Features

HY5PS1G831CFP-S6 features: (1)VDD = 1.8V +/- 0.1V; (2)VDDQ = 1.8V +/- 0.1V; (3)All inputs and outputs are compatible with SSTL_18 interface 8 banks; (4)Fully differential clock inputs (CK, /CK) operation; (5)Double data rate interface; (6)Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS); (7)Differential Data Strobe (DQS, DQS); (8)Data outputs on DQS, DQS edges when read (edged DQ); (9)Data inputs on DQS centers when write(centered DQ); (10)On chip DLL align DQ, DQS and DQS transition with CK transition; (11)DM mask write data-in at the both rising and falling edges of the data strobe; (12)All addresses and control inputs except data, data strobes and data masks latched on the rising ; (13)edges of the clock; (14)Programmable CAS latency 3, 4, 5 and 6 supported; (15)Programmable additive latency 0, 1, 2, 3, 4 and 5 supported; (16)Programmable burst length 4/8 with both nibble sequential and interleave mode; (17)Internal eight bank operations with single pulsed RAS; (18)Auto refresh and self refresh supported; (19)tRAS lockout supported; (20)8K refresh cycles /64ms; (21)JEDEC standard 60ball FBGA(x4/x8) , 84ball FBGA(x16); (22)Full strength driver option controlled by EMRS; (23)On Die Termination supported; (24)Off Chip Driver Impedance Adjustment supported; (25)Read Data Strobe supported (x8 only); (26)Self-Refresh High Temperature Entry.

Diagrams